1. Field of the Invention
This invention relates to manufacturing an integrated circuit, and more particularly, to filling a recess with a slurry to enhance reliability of the integrated circuit, the recess having been undesirably formed during fabrication of the integrated circuit.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon. An interlevel dielectric is then formed upon and between the interconnect routing, and more contact areas are formed through the dielectric to the interconnect routing. A second level of interconnect routing is placed upon the interlevel dielectric and coupled to the first level of interconnect routing via the contact areas arranged within the dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed if desired.
Unfortunately, unwanted recesses may form in the topological surface of one or more levels, or layers, employed by an integrated circuit. FIGS. 1-6 demonstrate the formation of such a recess. FIG. 1 depicts a semiconductor topography 10 having a shallow trench 12. Semiconductor topography 10 may be a single crystalline silicon substrate. Shallow trench 12 may be formed by etching away a portion of topography 10. A dielectric material 14, such as an oxide may then be deposited using chemical vapor deposition across the upper surface of topography 10 and into trench 12. Since dielectric material 14 is deposited at a relatively constant rate across the entire surface of topography 10, a recess 15 is formed in the surface of dielectric material 14 above trench
FIG. 2 illustrates using, e.g., chemical-mechanical polishing ("CMP") to remove dielectric material 14 from the upper surface of topography 10 except from within trench 12. A fill dielectric 16 having a relatively planar surface is thus formed within trench 12. Fill dielectric 16 may be used to separate doped regions of semiconductor topography 10, and therefore, the fill dielectric is oftentimes referred to as the field dielectric. If the shallow trench isolation area is large in area where fill dielectric is formed, certain problems can exist. For example, a large recess 15 may cause the CMP polishing pad to conform, under pressure, to the recess. This may enhance the previous recess 15 to that shown in FIG. 2 as recess 18.
A typical CMP process involves placing a semiconductor wafer face-down on a polishing pad which is fixedly attached to a rotatable table or platen. Elevationally extending portions of the downward-directed wafer surface contact with the rotating pad. A fluid-based chemical, often referred to as a "slurry" is deposited upon the pad possibly through a nozzle such that the slurry becomes disposed at the interface between the pad and the wafer surface. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The polishing process is facilitated by the rotational movement of the pad relative to the wafer (or vice versa) to remove material catalyzed by the slurry. Unfortunately, if the reaction rate of the slurry with the surface material varies across the surface, certain areas of the wafer may be removed more quickly than others. Also, as described above, a pad which conforms to the wafer, or bows in an arcuate pattern in response to force applied thereto, will undesirably remove some portions of the wafer while leaving others behind. Thus, reaction rate variation and/or pad pressure variation may lead to the formation of recess 18 of FIG. 2 in the upper surface of fill dielectric 16.
FIG. 3 depicts metal interconnects 19 disposed across an interlevel dielectric 15. Interconnects 19 extend are disposed in the same horizontal plane of an integrated circuit. Another interlevel dielectric 17 is formed across metal interconnects 19 by the deposition of a dielectric material, such as an oxide. Because interconnects 19 are closely spaced together, voids 21 form in the upper surface of interlevel dielectric 17 during the deposition step. The upper surface of interlevel dielectric 17 needs to be a pre-selected distance above the upper surfaces of interconnects 19 to meet design specification. Thus, since voids 21 extend downward and terminate below the upper surfaces of interconnects 19, CMP cannot be used to remove the voids.
Turning to FIG. 4, a semiconductor topography 20 is shown as having a conductive region 22 disposed within an upper portion of topography 20. Semiconductor topography 20 may be a silicon substrate or an interlevel dielectric, depending on the present stage of fabrication. Conductive region 22 may be a doped region within a silicon substrate or an interconnect within an interlevel dielectric. An interlevel dielectric 24 is formed across semiconductor topography 20 and conductive region 22. An opening 26 or "via" may be etched through interlevel dielectric 24 to conductive region 22. A conductive material 28 may be deposited across interlevel dielectric 24 and into opening 26, resulting in the formation of a recess 30 in the upper surface of conductive material 28 above opening 26. As shown in FIG. 5, a contact region or plug 32 is formed exclusively within opening 26 by using CMP to remove conductive material 28 form all areas except opening 26. Unfortunately, a recess 34 forms in the upper surface of plug 32 as a result of CMP. As described in U.S. Pat. No. 5,340,370 (herein incorporated by reference), the chemical species of CMP used to catalyze the conductive material may overly react with the material and cause recesses 34 within the material upper surface.
FIG. 6 illustrates yet another situation where recess formation is a problem. A plug 33 is formed upon a conductive region 23 that is disposed within a semiconductor topography 21. A conductive material, such as tungsten is deposited into an opening that extends vertically through an interlevel dielectric 25, resulting in plug 33. Unfortunately, during deposition of the plug material, a recess 35 forms in the upper surface of the plug that extends below the upper surface of interlevel dielectric 25. Such a recess may develop because deposition occurs at the same rate upon the bottom of the opening as upon the sides of the opening. Recess 35 cannot be removed by the CMP process because it extends below the surface of interlevel dielectric 25.
Alternatively, conductive material 28 may be removed using solely a chemical etchant. The chemical etchant may overly attack the conductive material when attempts to form a plug 34 of substantially planar upper surface. Accordingly, a recess 30 present in the upper surface of conductive material 28 before the etch process (see FIG. 4) is translated to a recess 34 in the upper surface of plug 34 post etch.
The above descriptions of the formation of recesses are only examples of many fabrication steps which might lead to recess formation. Such recesses may, among others, cause step coverage problems when layers of material are formed across surfaces having recesses. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. In general, the height of the step, e.g., the depth of the recess, and the aspect ratio of the features being covered, e.g., the depth to width ratio of the recess, affect the step coverage. The greater the step height or the aspect ratio, the more difficult it is to achieve coverage of the step without a corresponding thinning of the film that overlies the step. Furthermore, when a recess is present in a plug, the non-planarity of the surface of the plug may impair the ability to print high resolution lines during later photolithography steps. Thus, properly aligning interconnects to these plugs may be difficult. Additionally, a recess may cause the formation of voids or open circuits in the interconnects formed above the recess. Such disadvantages caused by plug recesses are even more of a problem when multiple layers are formed in which plugs with recesses overly each other.
It would therefore be desirable to develop a process for planarizing the surface of a structure employed by an integrated circuit. A process is needed which would obviate recesses upon the surface of either a conductive material or a dielectric. Such a process would provide for better step coverage and for better resolution of photolithography lines. The process would also inhibit shorting between certain structures separated by a fill dielectric.